1. Field of the Invention
The present invention relates to a display memory control apparatuses which is effectively used in information processing apparatuses such as various computers, in particular, in portable appliances in which it is important to lower the amount of power consumption.
2. Description of the Related Art
Information processing apparatuses such as a personal computer, a word processor and the like, have an image display device as a user interface. These information processing apparatuses are provided with a display memory (hereinafter, referred simply to as "VRAM") for storing data corresponding to an image. In the VRAM, a read for image display is regularly executed, and also, access from a central processing unit (hereinafter, referred simply as to "CPU") is irregularly executed. For this reason, access control is carried out by means of a display memory control circuit. In a conventional display memory control circuit, a periodical read access to the VRAM is preferentially executed in order to transmit display data to the display device. Therefore, in the case where the CPU makes an access to the VRAM, the CPU is in a wait state until timing other than the periodical read. Under such a control, the processing performance of CPU is not effectively exhibited, and this is one factor of lowering a processing speed.
FIG. 6 schematically shows the prior art which is disclosed in FIG. 1 of Japanese Unexamined Patent Publication JP-A 7-28990 (1995). As seen from FIG. 6, in the prior art, there are provided an address buffer 2 which stores a plurality of addresses at the time of writing from a CPU 1, and a data buffer 3 which stores a plurality of write data corresponding to these addresses. In order to control these address buffer 2 and data buffer 3, a buffer control circuit 4 is provided. A bus control circuit 5 executes control between each of the buffers and the CPU 1. The buffer control circuit 4 executes control for effectively writing the addresses and data stored in each of the address buffer 2 and the data buffer 3, into a VRAM 6.
In the prior art, the following proposal has been made. More specifically, a buffer for capturing write data to the VRAM 6 and addresses corresponding to the write data, is provided, and access control is made so as to obtain effective timing of writing the data in the VRAM 6. By doing so, it is possible to execute access processing without applying a load to the CPU 1 and depending upon the performance of VRAM 6. In a write sequence to the VRAM 6, first, when the bus control circuit 5 judges that the data is written from the CPU 1, the write data and address are stored in the data buffer 3 and the address buffer 2, respectively. At this time, the address and data mutually make one-to-one correspondence. The address buffer 2 informs the bus control circuit 5 about whether it is empty or full of the content stored as address, by using an internal control signal. And then, the bus control circuit 5 executes control between the CPU 1 and the VRAM 6 on the basis of the signal.
In the prior art, when the data is written in the VRAM 6 from the CPU 1, VRAM access is carried out the same number of times as CPU access; for this reason, the power of VRAM 6 itself is much consumed. Further, the required number of the address buffers 2 is equal to the number of data buffers 3; for this reason, this makes large a circuit scale, and also, is one factor of causing an increase in cost and power consumption. Further, in the case where a cache memory is applied as one method for speeding up a memory access, there is required a high speed buffer which can store data corresponding to a plurality of consecutive addresses; for this reason, it is inevitable that a circuit scale will be made larger, and that power consumption and cost will be increased.